Nonvolatile memories having higher integration density and larger storage capacity, and which are randomly accessible with address information, are increasingly regarded as important applications for mobile or mass storage devices. While known products for such nonvolatile memories are flash memories, there have been proposed other types, for example, ferroelectric random access memories (FRAM) using ferroelectric capacitors, magnetic RAMs (MRAM) using tunneling magneto-resistive films, and phase RAMs (PRAMs, phase-changeable RAMs, or chalcogenide-based RAMs) using chalcogenide alloys.
Specifically, the phase RAMs, which are capable of being fabricated with simple processing methods, provide larger storage capacity at lower cost, as well as the facilities of nonvolatile data retention. The phase RAMs are based on storage elements that use a class of materials which have the property of changing between two phases having distinct electrical characteristics. For instance, these materials may change from an amorphous, disorderly phase to a crystalline or polycrystalline, orderly phase, and the two phases are associated with considerably different values of resistivity.
At present, alloys of elements of group VI of the periodic table, such as Te (tellurium) or Sb (stibium), referred to as chalcogenides or chalcogenic materials, can be used in phase RAM cells. The chalcogenides that are widely used for storing data in overwrite disks are formed by a Ge (germanium), Sb and Te alloy (e.g., Ge2Sb2Te5; referred to as GST). Other chalcogenic alloys besides the GSTs are As—Sb—Te, As—Gb-Te, In—Sn—Sb—Te, Ag—In—Sb—Te, 5A group material-Sb—Te, 6A group material-Sb—Te, and 5A group material-Sb—Se. Nitrogen may be added to these compounds.
A phase RAM unit memory cell UC, as shown in FIG. 1, is composed of a variable resistor C connected to a bitline BL, an NMOS access transistor M connected between the variable resistor C and a ground voltage (or substrate voltage). A gate of the access transistor is coupled to a wordline WL. The variable resistor C, as shown in FIGS. 2A and 2B, includes a chalcogenide film GST, a top electrode TEC and a bottom electrode BEC between which the GST film is interposed. The top electrode TEC is connectively led to the bitline BL through a bitline contact BC while the bottom electrode BEC, made of a conductive material (e.g., TiN), is connected to a drain D of the access transistor M through a contact plug (or heater plug) CP. A crystalline condition of the chalcogenide film GST forming the variable resistor C is changeable by the current supply time and amount of current supplied thereto. A current path through the variable resistor C is formed between the bitline BL and the ground voltage when the access transistor M is turned on responding to an activation of the wordline WL.
The chalcogenide film material has two stable phases that are used to operate programming and erasing modes. As plotted by a curve 1 in FIG. 3, the chalcogenide material changes to an amorphous state if it is heated up above the melting temperature Tm (approximately 600° C.) for a time T1 and then quenched rapidly, which is referred to as a program (or reset) state for storing data “1”. As shown by a curve 2 in FIG. 3, the chalcogenide material moves to a crystalline state when it is quenched rapidly after it is heated to a temperature between the melting temperature Tm and the crystallization temperature Tc (approximately 450° C.) for a time T2 longer than T1, which is referred to as an erase (or set) state for storing data “0”.
Using the condition that an amorphous chalcogenide material has a relative resistance larger than that of a crystalline chalcogenide material, a voltage difference by a current passing through the variable resistor C determines data “1” or “0” in a read operation. A variable range of the relative resistivity in the chalcogenide material is about 103.
FIG. 4 illustrates an example of a memory cell array arranged in matrix form including chalcogenide unit cells. As shown in FIG. 4, the memory cell array of a phase RAM, like that of dynamic RAM, is constructed of unit cells UC coupled to bitlines BL0˜BLn-1 and wordlines WL0˜WLm-1 in a matrix pattern. Although not shown, each of the bitlines may be coupled to sense amplifiers.
Phase RAMs having the memory cell arrays shown in FIG. 4 should be more integrated because they may be most applicable to portable electronic devices such as mobile phones or personal digital assistants (PDAs), which require higher storage capabilities within restricted circuit areas.
In addition to the high integration needs, it also required to enhance current density throughout the chalcogenide film GST, which is a phase-changeable material film of the variable resistor. Current density is enhanced by concentrating current intensity on a heat point PTA where the bottom electrode BEC contacts the chalcogenide film GST. To increase the current density in the chalcogenide film GST, a diameter of the contact plug CP that acts as a heat medium actuated by the current should be smaller and a channel width of the access transistor M should be wider. Such restrictions on structural implementation may cause increasing dimensions of memory cell arrays due to inevitably larger channel widths of the access transistors, resulting in enlargement of chip sizes of high performance and high density phase RAMs. A layout area for a unit cell of a phase RAM, e.g., 6˜12F2, is wider that that of a normal DRAM. Therefore, there is a need to reduce the unit cell area in the phase RAM.